1. Field of the Invention
The invention relates in general to the automated design of integrated circuits, and more particularly, to design synthesis.
2. Description of the Related Art
Modern circuit design has evolved into a specialized field often referred to as electronic design automation in which computers and computer aided design (CAD) techniques are used to automate the integrated circuit (IC) design process. An IC design process typically begins with an engineer producing a high level design specification in terms of input/output signals, functionality and performance characteristics of a hardware circuit to be fabricated. These characteristics are captured in a high level hardware language model, which represents a design at a higher level of abstraction, which leaves unspecified many of the detailed elements of individual design objects that eventually a designer will need to consider. The designer then begins a process of incremental refinement, where he, often using a software-based tool, replaces highly abstracted elements of the design with more precisely specified elements that implement the same functionality. At each point he is making choices to implement the high level element in perhaps a way that will use less power than other ways, or use less space, or run more quickly, all according to his overall goals for the circuit.
Synthesis can be defined broadly as an automatic translation process from a description at higher level of abstraction to a description at a lower level of abstraction of the design,. The names commonly used in the field of IC design for the different levels of abstraction of design description are “behavioral”, “register transfer level (often abbreviated as RTL)”, “gate level netlist (also known as a structural design)” and physical (often called “GDS2”, based on the name of a standard language for such descriptions). A structural representation comprises a one-to-many mapping of a behavioral representation onto a set of components in accordance with design constraints such as cost, area, delay and power consumption. The structural design contains no layout information; that is introduced by the transformation to GDS2.
Each component in a structural design, in turn may be defined by its own behavioral description. Thus, a design can be represented at many different levels of abstraction, and different software-based synthesis tools typically are used depending upon the level of abstraction at which a design is specified, and the level at which a more refined design is desired For example, a system level synthesis tool may be used to translate a behavioral description at an algorithm or flow chart level to an RTL representation including components such as muxes, memories and buses. A register-transfer level synthesis tool may be used to translate a design description at the register transfer level to a structural representation including components such as gates and flip-flops, for example. Thus, design of an IC may involve multiple levels of synthesis. Synthesis sometimes is referred to as design refinement, since it adds an additional level of detail to a design that, in turn, provides information needed for the next level of synthesis or manufacturing process.
Generally, a more detailed design representation generated from a higher level representation by a synthesis-translation process must satisfy constraints supplied with the original high level design description or generated from a previous synthesis step. Constraints on design behavior, therefore, guide the synthesis of the design towards practical implementations in terms of factors such as performance, costs, testability and other physical restrictions. Physical constraints typically are specified separately from behavior either by declaration or in a separate file.
While prior approaches to synthesis generally have been acceptable, there have been shortcoming with their use. For instance, in the past users were required to created unique behavioral models for each desired implementation, even though the designs might be substantially similar Different implementations of a single behavioral design might include for example, a version designed to run at 500 MHz and use a 90 nanometer process, and one designed to run at 1 gigahertz, and use a 60 nanometer process. These two designs perform the exact same function, but because current state of the art RTL synthesis tools require substantially different designs in order to perform at these two performance points, user are required to maintain two different designs as input. As design requirements evolved in the course of the design process, users typically would implement these new requirements in each of the unique behavioral models.
FIGS. 1A-1B are illustrative drawings of a prior design processes 100, 102 in which each of two different behavioral models, representing different implementations of the same functionality, are modified to incorporate changed requirements. In FIG. 1A, a first input model 104 is provided as input to a software-based synthesis tool 106, which performs a synthesis-translation process and outputs a first output model 108, which is a lower level structural representation of the first input model 104. If the user wishes to produce another design similar to the design represented by the first input model 104, then the user copies and modifies the first input model 104 so as to produce a second input model 110. Modifications 112 may involve adding additional pipeline stages, replicating logic in multiple places because there is not sufficient time for the signal to propagate in the faster clock cycle design, as well as other tricks to enable a design to run in a shorter clock cycle in a faster process, for example. The second input model 110 is provided as input to a software-based synthesis tool 106, which performs the synthesis-translation process and outputs a second output model 114.
Referring to FIG. 1B, after the first and second models have been created as described with reference to FIG. 1A, a user may wish to fix a design flaw (i.e. a bug) or to enhance high level behavioral algorithm 105. In either case, the user must modify both the original first model to produce a revised first model 104a and to produce a revised second model 110a. The modified first input model 104a is provided as input to the synthesis tool 106, which outputs a modified first output model 108a. The modified second input model 104a is provided as input to the synthesis tool 106, which outputs a modified first output model 110a is provided as input to the synthesis tool 106, which outputs a modified first output model 114a. 
While this approach to the proliferation and modification of design models generally has been acceptable, there have been shortcomings with its use. For example, given the many design derivatives and modifications management of the design change process can quickly become complex and difficult to manage. As a result it has been difficult to migrate designs to different clock frequencies, limiting the ability to tailor a solution to high performance, high power environment, as well as lower power, cost-sensitive applications. Instead all but the most well funded designers must pick a middle of the road implementation, “good enough” for multiple uses, but not specifically suited to many one application space. Thus, there has been a need for improvements in the management of design changes and design derivative. The present invention meets this need.